Sometimes a single sentence can improve the channel loss of high-speed signals

                    Sometimes a single sentence can improve the channel loss of high-speed signals

Give you a scenario to think about: when the PCB design is completed and the plate lamination is determined, it has entered the state of launching the board. At this time, the simulation evaluation finds that the margin of high-speed signal channel may not be safe. Is there any chance to improve it?
 

Of course, the probability of this problem will not be very high, because since the simulation evaluation is to be carried out, the simulation verification work will certainly be put in front to determine whether the loss of the channel is OK in advance, to determine whether to use a better plate or take a wider line to reduce the loss. If you do run into a SI engineer who doesn't start simulation until the design is finished to evaluate the loss, Mr. High-speed will probably feel sad for you
 

But what do you do if you're unlucky enough to have a simulation engineer who tells you that the loss margin for high-speed signals might be a little low when you're ready to launch your design? At this time the laminators and plates have long been determined, device layout, wiring has been completed, you may need to be pushed down to redesign the probability has exceeded 95%, this time you look at this article, you may seize the remaining 5% possibility, say a simple word can improve the original is not enough loss!
 

What is the method of this article? Let's keep it a secret. First of all, let's take a look at the loss of our PCB wiring which is determined by the majority of ha!
 

 First we introduce the classification of PCB loss from the general direction. There are three kinds of losses: conductor loss, dielectric loss and radiation loss. You may listen to the first two more, the actual situation of PCB loss is mainly the previous two. As for the radiation loss, it is also related to the dielectric constant DK. In addition, the radiation loss basically only exists in the microstrip line, and if properly designed, it can be reduced to a relatively low level, accounting for a very small proportion in the total loss, which will not be introduced here.

The dielectric loss produced mainly by the dipole polarization phenomenon, so we don't like the habit of listening to too much theory, we put the theory to make a long story short, like the image below, the higher the frequency of applied voltage, so the greater the current, the oscillating dipole in material number, the more the value under the electric dipole, the greater the volume resistivity at the same time, the greater the The higher the power loss in the medium. To describe the material properties that measure the motion of the dipole, the concept DF was born

Let's talk about the other part, the principle of conductor loss. Must first know with an important concept in the theory, called the skin effect, in the high frequency current will along the surface of the conductor to run, which is at the time of high frequency, we resistance depends on the size of the current flows through the cross section size, current flows through the cross section is smaller, the greater the resistance, so the conductor loss is that increases with the increase of frequency

To sum up the loss factors mentioned above, that is, the plate mainly determines the medium loss, that is, we often say that the size of the plate DF has the greatest impact on the loss, and it is because of this reason that we distinguish the different grades of the plate. In addition, wire width and copper thickness affect conductor loss. The above said and our summary of the scene is very consistent, the plate is fixed, basically the medium loss is fixed, the lamination and design is fixed, the structure of the wire is fixed, the conductor loss is basically fixed. If we want to improve wastage in this case, we have to see if there are any other factors that can affect our wastage

Actually the loss also can go inside the conductor loss, and the principle is probably so, because of the skin effect, the current will be transfer in the copper teeth, as you go through the copper dental protrusions, compared to the slide of the copper surface, the transmission path of current get longer, so will further increase the dc and ac resistance at the same time, thus increasing the conductor losses
 

We are familiar with several types of copper foil with different roughness grades, including ordinary STD copper foil, RTF reversed copper foil and HVLP ultra-low profile copper foil, of course, now there are HVLP2 and HVLP3 copper foil which continue to optimize on the basis of HVLP copper foil. But the reality is that many friends know that different roughness of copper foil will affect the loss, but do not know how much impact, can there be quantitative data to give. We actually think about it is not easy, not easy point is that the loss is composed of several large parts, mainly including plate DF, line width and copper thickness, reference layer thickness and now said copper foil roughness. If you want to separate out the effect of different types of copper foil roughness, then you must ensure that the factors are consistent in order to simply extract. To be specific, it is necessary to ensure that the plate is the same, the wiring structure is the same, and the wiring reference thickness is the same. Only the copper foil roughness is different, the influence of copper foil roughness can be known separately. Do you think it's possible?

\Mr. High-speed makes HVLP and RTF copper foil respectively in the upper and lower parts of the same laminade. Because the upper and lower parts are symmetrical, the wiring structure and the thickness of the medium are exactly the same. In addition, the same laminade means that the plate is the same and the same processing, so there will be no processing error. This can be done successfully because the wiring layer of the specified RTF and HVLP copper foil is the same length.

Just like this test board, we took the wiring of RTF and HVLP copper foil on L5 layer and L12 layer respectively, and the length of the wiring was the same (the length of the wiring was 3inch after the embedding was removed). Therefore, except for the roughness of the copper foil, other factors could be guaranteed to be the same. In this case, the wiring test of the two pairs was carried out. The influence of two different copper foil roughness on loss can be obtained by pure comparison

This article is quite a long one. First of all, we analyze several major factors that cause PCB loss in theory. Then we share a test method of how to separately extract the influence of different copper foil roughness on the loss, so as to quantitatively obtain the influence degree of different roughness on the wire loss.