PCB design Power supply plus magnetic beads (II)

To avoid the tedious study of formulas, let's take a look at the actual simulation results.

In order to facilitate the research, a simulation case is designed, as shown in Figure 1: CaseE1 is the capacitor placed near the chip pin, and Case1B is the capacitor placed far away from the chip pin.

At this time, Case1B has one more pair of power supply ground pass holes than Case1. In order to compare the position influence of capacitance only under the same conditions, we add Case1a case, and add a pair of power supply ground pass holes at the same position as Case1B capacitor Fan out.

Layers 4 and 5 are the plane of power supply coupling.

First, let's take a look at the situation when the power source ground distance is 3mil: when the power source is tightly coupled, the PDN curves of Case A and B basically coincide, indicating that the resonant frequency of the capacitor does not change.

That is to say, the position of the capacitor seems to have almost no effect, but the resonant frequency of Case1 is inclined to the low frequency, indicating that the installed inductance of Case1 is larger.

This is easy to understand, mainly out of a pair of power supply ground hole.

When the distance between the power source and ground is within 10mil, the above conclusions are similar.

But when the distance between the power source and the ground is 20mil or even 50mil, the situation changes slightly.

As shown in Figure 3, when the distance between the power source and ground increases, the PDN curves of Case A and Case B begin to deviate, and the resonant frequency of Case1B shifts to low frequency, indicating that when the capacitor is far away from the chip pin, the installation inductance of the capacitor becomes significantly larger.

We can draw a simple conclusion:

Typical 8 or more layers of single board, or 6 layers of board using 3 power supply ground plane, power supply ground relatively tight coupling design, at this time the filter capacitor on the board presents "global characteristics", that is to say the position of the capacitor is not very "important", the capacitor in the global role.

When the distance between the power source of the double panel and the four-layer plate and the six-layer plate is relatively long, the filter capacitor on the plate tends to be "local characteristic". The position of the capacitor is more important, and it is best to place it close to the chip pin.

When the power supply network is not designed using the power supply ground plane, capacitors tend to be "local characteristics".

For example, the capacitance of PLL power supply, such as the capacitance of VREF power supply in the design of DDR3, all want to strictly put the corresponding capacitance close to the chip pin, or even it is best to do the design to specify that the power supply must enter the chip pin from the filter capacitor.

Similarly, for conventional digital power supply, such as 3.3V, 2.5V IO power supply, if we use magnetic bead isolation for each chip and separate power supply, then the capacitor will lose the "global" function.

One of the most immediate negative effects is the need to add more filter capacitors to the design.

Or the number and type of capacitors on a chip is not enough, resulting in the power track noise.

Even if the number of capacitors is not an issue and the power supply noise is controllable, "misusing" the beads can cause other design problems.

The third option in Figure 4 is the very popular 12-layer laminated design.

The main reason why we choose such a cascade is that the segmentation of the power supply is too broken. If such a power supply layer is used as a reference plane, it will be more difficult to avoid the "cross-segmentation" problem (single-sided cross-power segmentation problem, we will have a special discussion).

Layering of scheme three avoids the problem of multiple power supply segmentation, but brings more severe interlayer crosstalk and other problems.

The variety of power supply is the status quo of design, "misuse" of magnetic beads will "add insult to injury" to the variety of power supply.

Increase the difficulty of power plane design.

The addition of magnetic beads, however, does not actually benefit the power supply noise.

Summary: In conventional digital power supplies, where multilayer design is used and the power ground plane is tightly coupled, it is not recommended to "abuse" the magnetic beads and keep the "global" characteristics of the capacitance in effect.

There are two kinds of occasions where magnetic beads are needed

1. "Special" protection, such as PLL power supply, etc

2. Caring for others, having strong interference, avoiding EMI problems, such as clock chips with strong drive, etc

At the end of a topic, you always feel like you don't have any questions to ask because you think you've made everything clear.

But what about every time the editor highlights "your problem"?

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