29 PCB Design Mistakes

Misunderstanding one, cost saving

Common Mistake # 1: What color is the indicator light on the panel?

Personally, I prefer blue, so I'll take it

Positive solution: for the indicator light on the market, red, green, yellow, orange and other colors, regardless of the size (5MM), packaging, have been mature for decades, so the price is generally less than 5 cents.

And the blue indicator light is nearly three or four years before the invention, technology maturity and supply stability are poor, so the price is four or five times more expensive.

If you don't have a specific color requirement for the panel stack indicator, don't choose blue.

At present, the blue indicator light is generally used only in the situation that cannot be replaced by other colors, such as the display of video signals.

Common Mistake # 2: It doesn't seem to matter how much resistance you use for these low/high resistors, just pick an integer of 5K

Positive solution: In fact, there is no 5K resistance value on the market, the closest is 4.99K (accuracy 1%), followed by 5.1K (accuracy 5%), the cost of 4.7K is 4 times and 2 times higher than the accuracy of 20%, respectively.

20% precision resistance value only 1, 1.5, 2.2, 3.3, 4.7, 6.8 a few kinds (including integer multiple of 10);

Correspondingly, the capacitance of 20% accuracy is the same with only the above capacitance values.

For resistors and capacitors, if you choose values other than these, you have to use higher precision, which multiplies the cost several times. If the accuracy is not very high, this is a waste of cost.

Common mistake 3: this logic with 74XX gate circuit is also good, but too soil, or use CPLD, it seems much more upscale

The 74XX gate circuit is only a few cents, and the CPLD is at least dozens of pieces (GAL/PAL although only a few dollars, but not recommended to use), the cost has increased many times, but also the production, documentation and other work to add several times the work.

Under the premise of not affecting performance, the use of more cost-effective 74XX is obviously more appropriate.

Common mistake 4: the PCB design of this board is not high, so use a thin line and automatically cloth it

Truth:

Automatic wiring is bound to occupy a larger PCB area and produce many times more through holes than manual wiring. In terms of pricing of products with a large batch, PCB manufacturers will consider the line width and the number of through holes as important factors, which respectively affect the PCB yield and the amount of bit consumption.

In addition, the area of PCB board also affects the price.

So automatic wiring is bound to increase the production cost of the circuit board.

Common Mistake # 5: Our system is so demanding that all the chips, including MEM, CPU, FPGA, etc., have to be the fastest

Pro: In a high-speed system, not everything works at high speed, and the price almost doubles for each level of device speed, with a significant negative impact on signal integrity.

So, when choosing a chip, you need to think about how much different parts of the chip will be used, not just the fastest one.

Common Mistake # 6: As long as the program is stable, the code is long and inefficient, not the key

Pro: CPU speed and memory space can be bought with money. If you spend a few more days writing code to improve the efficiency of your program, the cost savings from reducing CPU frequency and memory capacity will be worth it.

CPLD/FPGA designs are similar.

Myth 2: Reliability design

Common mistake 7: this single board has been small batch production, after a long time of testing did not find any problems, do not need to look at the chip manual

Positive Solution: Hardware design and chip application must comply with relevant specifications. In particular, all parameters mentioned in the chip manual (voltage resistance, I/O level range, current, timing, temperature PCB wiring, power quality, etc.) must be strictly set and cannot be verified by only testing.

A lot of companies have many products have painful lessons, the product sold a year or two, IC manufacturer changed a production line, the board does not turn, the reason is that the chip parameters of the others have a little change, but did not exceed the scope of the manual.

If you follow the manual, then he is not afraid of any changes, if the parameters become out of the manual range can also ask him for compensation (if you can still rotate the board, then your reliability is more cattle).

Common Mistake # 8: You can't blame me for user action errors

It is correct to require users to operate strictly according to the manual, but users are human beings and they will make mistakes. We cannot say that if we touch the wrong key, the machine will crash and if we plug in the wrong plug, we will burn the board.

Therefore, all kinds of mistakes that users may make must be anticipated and protected in advance.

Common mistake 9: the reason why this board is bad is the board on the end of the problem, also not my responsibility

Correct solution: there should be enough compatibility for all kinds of external hardware interface, can't because the other side signal is not normal, you completely strike.

It should only affect the part of the function related to it, and the other functions should work properly, should not be completely out of action, or even permanently damaged, and you should restore the interface as soon as it is restored.

Common Mistake # 10: This part of the circuit is fine as long as software is required to design it this way

Truth: Many of the features of hardware devices are directly controlled by software, but software is often buggy, and there is no way to predict what the program will do when it flies.

The designer should ensure that no matter what operation the software is doing, the hardware should not be permanently damaged in a short time.

Myth 3: System efficiency

Common Mistake # 11: Do you use interrupts or queries for so many tasks?

Let's cut it off quickly

Positive solution: Interrupts are real-time, but not necessarily fast.

If the interrupt task is too many, this one does not exit, and then one after another, after a while the system will crash.

If task number but very frequent, have spent a lot of pass in and out of the CPU interrupt on the overhead of the system efficiency is very low, if use query method can greatly improve efficiency instead, but sometimes can not meet the requirement of the real-time performance, so the best way is to query in the interrupt, namely into an interrupt is the accumulation of all the tasks are processed out again.

Common Error # 12: The CPU with a 100M primary frequency can only handle 70% of the CPU. The CPU with a 200M primary frequency will be fine

The processing capacity of the system involves a variety of factors, in the communication business its bottleneck is generally in the memory, no matter how fast the CPU, external access is not fast up is also futile.

Common Mistake # 13: The CPU using a larger CACHE should be faster

In some cases, it may be faster to disable the CACHE than to use it.

The reason for this is that data moved into the CACHE must be reused several times to improve system efficiency.

Therefore, in the communication system, only instruction CACHE is opened, and even if the data CACHE is opened, it is limited to part of the storage space, such as the stack part.

It also requires the program design to take into account the size of the CACHE and the size of the block. This involves the length and jump range of the key code loop body. If a loop is just a little larger than the CACHE, it is troublesome to loop through it again and again.

Common error 14: memory interface timing is the manufacturer's default configuration, do not need to change

Positive solution: the default value of the memory interface set by the BSP is set according to the most conservative parameter. In practical application, it should be reasonably adjusted by combining the parameters of the bus working frequency and waiting period.

Sometimes reduce the frequency can improve the efficiency, such as RAM access cycle is 70ns, bus frequency is 40M, set the access time of 3 cycles, namely 75ns can be;

When the bus frequency is 50M, it must be set to 4 cycles, but the actual access time slows down to 80ns.

Common Mistake # 15: This CPU has a DMA module, which is a fast way to move data

True solution: The real DMA is when the hardware preempts the bus and starts both devices at the same time, reading this side and that side in a cycle.

However, many DMA embedded in the CPU is just simulation. Before starting each DMA, we need to do a lot of preparation work (setting the initial address and length, etc.). During transmission, it is often read to the chip for temporary storage first and then write out again.

There is no loop jump and so on), but if you only move a few bytes at a time, you have to do a lot of preparatory work, usually involving function calls, which is not very efficient.

So this kind of DMA is only suitable for large data blocks, don't use it blindly.

Common error 16: a CPU processing can not come over, use two distribution processing, processing capacity can be doubled

Truth: When it comes to lifting bricks, two men should be twice as efficient as one.

When it comes to painting, having an extra person doesn't help.

The use of several CPUs requires more understanding of the business to determine, that is to say, to minimize the cost of coordination between the two CPUs, so that 1+1 as close as possible to 2, never less than 1.

Myth 4: Low power design

Common mistake 17: These bus signals are pulled with a resistor, feel relieved

Truth: There are many reasons why a signal needs to be pulled up and down, but not all of them.

Pull up and down resistor to pull a simple input signal, the current is tens of microampere below, but pull a driven signal, its current will reach milliampere level, now the system is often 32 bits each address data, there may be 244/245 isolated after the bus and other signals, pull up,

A few watts of power is consumed by these resistors (don't think of those watts in terms of 80 cents per kilowatt; see below for the reasons).

Common Mistake # 18: Our system is powered by 220V, so we don't need to worry about power consumption

Positive solution: Low power design is not only to save electricity, but also to reduce the cost of the power module and the cooling system, and to reduce the interference of electromagnetic radiation and thermal noise due to the reduced current.

As the temperature of the device decreases, the life of the device is extended correspondingly (the life of the semiconductor device is reduced by half for every 10 degree increase in the operating temperature of the device).

Power consumption is always a consideration.

Common Mistake # 19: The power consumption of these small chips is too low to be considered

Truth:

For chips with less internal complexity, power consumption is difficult to determine. It is mainly determined by the current on the pins. An ABT16244 consumes less than 1 mA without load, but its index is that each pin can drive a load of 60 mA (such as matching a resistance of several tens of ohm).

That is, the maximum power consumption of the full load can reach 60*16=960mA. Of course, only the power supply current is so large that the heat falls on the load.

Common Mistake # 20: What to do with these unused I/O ports on the CPU and FPGA?

We can leave it empty for later

Positive solution: if the unused I/O port is suspended, a little interference from the outside world may become a repeatedly oscillating input signal, and the power consumption of MOS devices basically depends on the number of gate circuit turnover.

If you pull it up, each pin will also have a microampere level of current, so the best way is to set the output (of course, the outside can not be connected to other driven signals).

Common Mistake # 21: There are so many doors left in this FPGA that you can use them

Positive solution: The power consumption of the FGPA is proportional to the number of triggers used and the number of flips, so the power consumption of the same type of FPGA in different circuits at different times may be 100 times different.

Reducing the number of high speed flip triggers is the fundamental method to reduce FPGA power consumption.

Common error 22: there are so many control signals in the memory, I only need to use the OE and WE signals on this board, choose to ground it, so that the data will come out much faster during the read operation

Positive solution: the power consumption of most memory will be more than 100 times greater when the chip selection is effective (regardless of OE and WE) than when the chip selection is not, so CS should be used to control the chip as much as possible, and the width of the chip selection pulse should be reduced as much as possible if other requirements are met.

Common Mistake # 23: Reducing power consumption is all about the hardware people, not the software

Truth:

The hardware just sets the stage, but the software plays the role. Almost every chip access and every signal flip on the bus is controlled by the software.

Reducing the number of visits to external memory (more use of register variables, more use of internal caches, etc.), responding to interrupts in a timely manner (interrupts are often low level and have pull-up resistors), and other specific measures for specific boards will contribute significantly to reducing power consumption.

Want the board to turn well, the hardware and software must grasp both!

Common Mistake # 24: Why are these signals overshot?

As long as it's a good match, it can be eliminated

Positive solution: Except for a few specific signals (such as 100base-t, CML), all signals are overshot. As long as they are not very large, they do not necessarily need to match, and even if the match is not the best match.

As TTL output impedance is less than 50 ohms, or even 20 ohm, if in such a big match their resistance, the current is very big, power consumption is unacceptable, and signal amplitude will be too small to use, say average output signal in the output of high level and low output impedance of electricity at ordinary times not the same, also do match exactly.

Therefore, TTL, LVDS, 422 signal matching as long as the overshoot can be accepted.

Myth 5: Signal integrity

Common Mistake # 25: These signals have been simulated and must be fine

Correct solution: the simulation model cannot be exactly the same as the real thing, even different batches of processing of the real thing are different, let alone the model.

And the reality is so different that simulations can't exhaust all the possibilities, especially cross-talk.

One lesson learned is that packets of a certain length on a single board are very easy to lose. The last reason is that the value of the length field is 0xFF. When this data appears on the bus, it interferes with the adjacent WE signal and cannot be written to RAM.

Other data also interferes with the WE, but within acceptable limits, but when the 8-bit bus is divided from 0 to 1 at the same time, nearby signals become overwhelmed.

The conclusion is that the simulation results are only for reference, and enough allowance should be left.

Common Mistake # 26: To ensure a clean power supply, more uncoupling capacitance is better

Positive solution: in general, the more uncoupling capacitors the power supply will of course be smoother, but too much also has disadvantages: waste cost, wiring difficulties, charging impact current is too large, and so on.

The key to the design of the de-coupling capacitor is to choose the right capacity and put it in the right place. The general chip manual has the design reference for the de-coupling capacitor. It is best to do it according to the manual.

Common Mistake # 27: Since it's a digital signal, the steeper the edge, the better

Positive solution: the steeper the edge, the wider the spectrum range, the higher the energy of the high frequency part;

The higher the frequency, the more easily it radiates (microwave radio can be used as a mobile phone, but long wave radio cannot be used in many countries), the more easily it interferes with other signals, and the poorer the quality of its transmission over the wire.

So those who can use low speed chips can use low speed chips as much as possible.

Common mistake 28: Signal matching is really troublesome, how to match well?

Positive solution: generally speaking, the reflection of the signal becomes important when the transmission time of the signal on the wire exceeds its jump time.

The reflection of the signal is caused by the non-uniform impedance of the line. The purpose of matching is to make the impedance of the driver end, the load end and the transmission line close. However, the good matching is also closely related to the topology structure of the signal line on the PCB.

On a transmission line is one of the branches, a through hole, a corner, a connector, different locations and change of ground distance will make the impedance changes, and these factors will make reflection waveform is complicated, it is difficult to match, so the way of high-speed signal using only the point-to-point, as much as possible to reduce the hole and corner.

Common error 29:100M data bus should be considered high frequency signal, as for this clock signal frequency is only 8K, it is not a problem

Truth:

The value of the data bus is generally by the control signal or an edge of the clock signal sampling, as long as the struggle for the edge to keep sufficient settling time and keep time, interference or overshoot outside this range will not have much impact (overshoot, of course, had better not exceed chip can withstand maximum voltage value),

However, no matter how low the frequency of the clock signal is (in fact, the spectrum range is very wide), its edge is the most important, and its monotonicity must be guaranteed, and the jump time must be within a certain range.